SMART CEO and Director Professor Eugene Fitzgerald discusses the economic and social impact of creating silicon technologies that are able to penetrate new markets, and why innovation in deep tech is necessary to create intellectual capital to attract investment.
By Professor Eugene Fitzgerald
For 55 years, Moore’s Law has enabled the pace of technology development by doubling the density of transistors in chips roughly every two years. Over the decades, this has enabled performance to grow by multiples while the cost of the physical components has fallen. More recently, the semiconducting silicon chip, which underpins nearly everything in our digital world, has been pushed to its limits.
The number of transistors that can be placed on a single chip has grown exponentially from a single one in 1947 to tens of billions today. However, the diameter of an individual silicon atom, at around 0.2 nanometers, puts a ceiling on the number that can be placed in circuits, the smallest of which in production measures just 5 nanometers in width. More importantly, though, is that pushing these limits further will not produce profit for those few companies that invest in this diminishing future.
Without the ability to reduce the size of integrated circuits further, we cannot continue to produce the gains we have made through silicon during this remarkable era of technology development. Meeting the performance increments necessary for the next generation of electronic systems requires new ways of thinking on how we manufacture devices, centering on exploring materials that perform better than silicon itself.
After nine years of research at the Singapore-MIT Alliance for Research and Technology (SMART), Massachusetts Institute of Technology’s only research enterprise outside the United States, we are able to show a new direction in silicon that will allow a new era of advancements.
The Low Energy Electronic Systems (LEES) research group I lead has spent this time looking at how future integrated circuits of value will be built and how we can incorporate novel materials that will bring new capabilities in silicon integrated circuits.
The research community has accepted that there will no longer be any more gigantic advances in silicon chips, which have so far provided the platform for all the huge leaps technology has made in recent generations. These have supported everything from cellphones to satellites, but their limitations are now becoming apparent.
When we proposed the LEES initiative 10 years ago, our objective was to enable the integrated circuits of the future that would gain the same generational advantages that we have become accustomed to, albeit in a different way. We saw from the start that the chips we needed to develop should improve systems through better communication and as interfaces between machines and people.
Such improvements would be used to facilitate the formation of new markets like 5G wireless networks, augmented reality and virtual reality, in which communication between technology and humans would determine the value of a system.
Our unique approach, which placed innovation front and center as part of a long-term strategy, allowed us to step away from the traditional method of development that only considered technology advances in isolation, in terms of computing power and memory. Instead, we have been able to factor in simultaneously the market, cost and technology performance goals throughout our process.
Critically, we recognized from the beginning the need for any new technologies to be supported by the current silicon integrated circuit ecosystem and its manufacturing infrastructure.
With silicon computing saturating, the key to the future is interconnecting with other systems wirelessly and at lower power. 5G, for example, enables very high bandwidth wireless networks which can call on several microprocessors over long distances so that communication occurs at great speeds.
Developing circuits that could easily unleash this kind of performance at a time when silicon alone is running out of horsepower will enable us to open up new markets that require processing might, that has until now not been available beyond our theoretical calculations. However, the cost of producing an entirely new category of materials from scratch, no matter how powerful they might be, would be prohibitive and prevent any real return on investment. This is why my team at LEES has set out to develop a means to use materials that leverage existing invested infrastructure—the huge plants that supply and manufacture silicon—to provide the foundations.
Our work on III-V devices does just that, and we expect it to provide the kind of exponential economic growth that we have seen in past pure silicon chips while simultaneously lowering costs and creating new markets—our initial objectives when we first considered the purpose of our group.
These III-V devices use materials that combine elements from the third and fifth columns of the periodic table, such as gallium arsenide or gallium nitride. These have shown particularly high performance in exacting communications and human interfaces when combined with existing silicon circuits.
Last year, we announced a manufacturing process to put these new III-V devices into silicon circuits, and recently we have been able to demonstrate the first circuits made in this way within a silicon manufacturing infrastructure.
A common silicon circuit takes a wafer, on which silicon transistors are printed on the surface of the front end. We have leveraged this traditional design by merging new wafers with III-V transistors and interconnecting them with silicon transistors through the same backend that is used in chip manufacturing today. Through this approach, we end up with new, higher-powered and increased functional silicon circuits that offer many more advantages than can be had with silicon alone. These boosted circuits open up a wealth of opportunities.
The first markets for their use will involve pixelated light engines—tiny arrays of LEDs powered by silicon circuits on a silicon chip. The devices have many other applications, such as in the consumer automotive, AR and VR space. In terms of vital communications, III-V devices will be able to fully optimize the benefits of 5G while also lowering costs.
Our ability to have such commercialization potential today could have only occurred through long-term research performed with the innovation process at SMART. The beauty of the SMART model is that it allows researchers at MIT and SMART to initiate collaboration over a long timeframe by working with many researchers in Singapore that are interested in the project. It allows us to start with an expansive research theme that requires many different disciplines to work together with the resources they need to develop a viable product at the other end that will be commercialized.
In this specific case of LEES and the new integrated circuits we have arrived at, we have formed a new company, New Silicon Corporation, to take this technology to market. This is a fabless company, and so it takes away the need to build new infrastructure by calling on existing players to carry out production.
The partners are just as excited as us about the potential of these III-V devices, which they will manufacture alongside the traditional silicon chips. New Silicon Corporation designs integrated circuits and has these partners manufacture the circuits with New Silicon Corporation’s proprietary intellectual property to make new products.
Instead of shrinking transistors in the future, we are going to add these new powerful III-V devices at an exponential rate to silicon chips and power applications that will allow us to continue on a different path to improve systems, a different path than Moore’s Law.
Altogether, this shows the power of an interdisciplinary organization like SMART, which has allowed us to go from something that has been dreamed about for the last 40 years to become a real embodiment after years of research. We have a truly unique environment that allows us to go from a starting point of high research uncertainty to commercialization. We have been able to pull in all the best researchers in Singapore to work with MIT investigators in this process of translation as it unfolds.
Based on our commercialization plans at New Silicon Corporation, we expect to see these new chips to begin production a year and a half after the next round of funding, while full production will come in two to three years. These are timelines that could not be achieved if we did not have the SMART LEES program running for nine years.
We are witnessing the start of a new silicon industry in which III-V devices inserted into silicon circuits will bring new features, more efficiency, and high-power to systems we will rely on as technology develops. These III-V devices added to a silicon design environment have indeed enabled a whole new set of integrated circuits for the future, truly making silicon great and new again.
(Ed. Professor Eugene Fitzgerald is CEO and Director of Singapore-MIT Alliance for Research and Technology (SMART), MIT’s research enterprise in Singapore. Professor Fitzgerald is also Lead Principal Investigator for SMART’s Low Energy Electronic Systems interdisciplinary research group. His latest venture is New Silicon Corporation, which has created a commercially suitable way to incorporate III-V elements into silicon wafer, to accelerate the chip development needed for 5G and Silicon III-V technology. Professor Fitzgerald is also a professor in Materials Engineering at MIT and co-author of the book ‘Inside Real Innovation’. Featured image by Photographer Miguel Á. Padriñán.)